The invention relates generally to electronic memory devices used as data buffer temporarily storing digital data transmitted between two different devices.
Data buffers are known for providing temporary storage of transmitted data to eliminate inefficiencies when the data source or data receiver is idle while waiting for the other. A data buffer, by smoothing the transmission rate of data intermittently transmitted or received, increases the efficiency of data flow. Data buffers are used to accommodate continuous data flow where the data source and data receiver have different data rates.
For high speed data buffering, it is known to use a Dual-Port, Static Random Access Memory (DPSRAM) which operates analogously to standard computer memory, allowing reading or writing in arbitrary order of a number of memory addresses, but with the additional feature that independent reading and writing can occur through separate ports. When a DPSRAM is used as a data buffer, data is written through one port at first address locations, while data is read through a second port from different address locations. Data may be written to and read from the DPSRAM at different rates. On such DPSRAM data buffer is commercially available from the assignee of the present application, GENROCO, Inc., under the tradename of TURBOstor.RTM., and is the subject of U.S. Pat. No. 5,420,984 hereby incorporated by reference.
The dual ports of the DPSRAM eliminates the delay implicit in sharing addressing resources between the input and output, but the random access nature of the DPSRAM introduces some delays because addresses for each word of data must be generated prior to transmitting that word, to identify the location of the data being read from or written to the DPSRAM. Nevertheless, the DPSRAM architecture is extremely flexible and intuitive.
An alternative data buffer design uses a first-in-first-out (FIFO) register in which data is entered into an input of the register and may independently be read out of the output of the register, in the same order in which it was entered. Transferring data into and out of a FIFO register can be extremely rapid because the data is entered and accepted in serial fashion, and thus addressing delays are avoided. Yet, despite the speed advantage of a FIFO register, it is relatively inflexible and may be cumbersome for certain types of data transfer where the data is not sequential. Further, for certain data receiving devices, the amount of data held in the buffer (word count) must be known prior to reading it out. If this information is known only after the buffer is filled, in a FIFO buffer, the word count must be placed in a trailing position, not accessible to the reading device. Finally, monitoring data latency, i.e., how long it takes the data to pass through the buffer, is difficult in a FIFO system.
Ideally, the good features of a FIFO and DPSRAM data buffer could be realized in one device.